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1/11 september 2002 n one input and two output buses n unlimited expansion in bit and word direction n data lines have latched inputs n 3-state outputs n separate control of each bus, allowing simultaneous independent reading and any of four registers on bus a and bus b and independent writing into any of the four registers n 40208b is pin-compatible with industry type mc14580 n standardized, symmetrical output characteristics n quiescent current specif. up to 20v n 5v, 10v and 15v parametric ratings n input leakage current i i = 100na (max) at v dd = 18v t a = 25c n 100% tested for quiescent current n meets all requirements of jedec jesd13b "standard specifications for description of b series cmos devices" description hcf40208b is a monolithic integrated circuit fabricated in metal oxide semiconductor technology available in sop packages. hcf40208b is a 4 x 4 multiport register containing four 4-bit registers, a write address decoder, two separate read address decoders, and two 3-state output buses. when the enable input is low, the corresponding output bus is switched, independently of the clock, to a high impedance state. the high impedance third state provides the outputs with the capability of being connected to the bus lines in a bus organized system without the need for interface or pull-up components. when the write enable input is high, all data input lines are latched on the positive transition of the clock and the data is entered into the word selected by the write address lines. when write enable is low, the clock is inhibited and no new data is entered. in either case, the contents of any word may be accessed via the read address lines independent of the state of the clock input. hcf40208b 4 x 4 multiport register pin connection order codes package tube t & r sop hcf40208bm1 HCF40208M013TR sop
hcf40208b 2/11 input equivalent circuit pin description functional diagram pin no symbol name and function 4, 5, 6, 7 q0a to q3a word a output 22, 23, 2, 1 q0b to q3b word b output 20, 19, 18, 17 d0 to d3 data inputs 16 clock clock input 15 write enable write enable input 21 3-state b 3 state output 3 3-state a 3 state output 8, 9 write 0, write 1 write address inputs 10, 11 read 0b, read 1b read address inputs 13, 14 read 0a, read 1a read address inputs 12 v ss negative supply voltage 24 v dd positive supply voltage
hcf40208b 3/11 logic diagram
hcf40208b 4/11 schematic diagram
hcf40208b 5/11 truth table timing chart absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied. all voltage values are referred to v ss pin voltage. clock write enable write 1 write 2 read 1a read 0a read 1b read 0b enable a enable b dn dna qnb h s1 s2s1s2s1s2 h h h h h h s1 s2s1s2s1s2 h l l l l x x xxxxxx l l z z z hlllhhlhh dn to word 0 word 1 out word 2 out llllhhlhh word 0 not altered word 1 out word 2 out x xxxhllhhxx word 2 out word 1 out x xxxxxxhhxncnc symbol parameter value unit v dd supply voltage -0.5 to +22 v v i dc input voltage -0.5 to v dd + 0.5 v i i dc input current 10 ma p d power dissipation per package 200 mw power dissipation per output transistor 100 mw t op operating temperature -55 to +125 c t stg storage temperature -65 to +150 c
hcf40208b 6/11 recommended operating conditions dc specifications the noise margin for both "1" and "0" level is: 1v min. with v dd =5v, 2v min. with v dd =10v, 2.5v min. with v dd =15v symbol parameter value unit v dd supply voltage 3 to 20 v v i input voltage 0 to v dd v t op operating temperature -55 to 125 c symbol parameter test condition value unit v i (v) v o (v) |i o | ( m a) v dd (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. i l quiescent current 0/5 5 0.04 5 150 150 m a 0/10 10 0.04 10 300 300 0/15 15 0.04 20 600 600 0/20 20 0.08 100 3000 3000 v oh high level output voltage 0/5 <1 5 4.95 4.95 4.95 v 0/10 <1 10 9.95 9.95 9.95 0/15 <1 15 14.95 14.95 14.95 v ol low level output voltage 5/0 <1 5 0.05 0.05 0.05 v 10/0 <1 10 0.05 0.05 0.05 15/0 <1 15 0.05 0.05 0.05 v ih high level input voltage 0.5/4.5 <1 5 3.5 3.5 3.5 v 1/9 <1 10 7 7 7 1.5/13.5 <1 15 11 11 11 v il low level input voltage 4.5/0.5 <1 5 1.5 1.5 1.5 v 9/1 <1 10 3 3 3 13.5/1.5 <1 15 4 4 4 i oh output drive current 0/5 2.5 <1 5 -1.36 -3.2 -1.1 -1.1 ma 0/5 4.6 <1 5 -0.44 -1 -0.36 -0.36 0/10 9.5 <1 10 -1.1 -2.6 -0.9 -0.9 0/15 13.5 <1 15 -3.0 -6.8 -2.4 -2.4 i ol output sink current 0/5 0.4 <1 5 0.44 1 0.36 0.36 ma 0/10 0.5 <1 10 1.1 2.6 0.9 0.9 0/15 1.5 <1 15 3.0 6.8 2.4 2.4 i i input leakage current 0/18 any input 18 10 -5 0.1 1 1 m a i oz 3-state output leakage current 0/18 any input 18 10 -4 0.4 12 12 m a c i input capacitance any input 5 7.5 pf
hcf40208b 7/11 dynamic electrical characteristics (t amb = 25c, c l = 50pf, r l = 200k w , t r = t f = 20 ns) symbol parameter test condition value (*) unit v dd (v) min. typ. max. t phl t plh propagation delay time clock or write enable to q 5 360 720 ns 10 140 280 15 100 200 propagation delay time read or write address to q 5 300 600 ns 10 120 240 15 85 170 t pzh t phz 3-state disable delay time 5 100 200 ns 10 50 100 15 40 80 t pzl t plz 3-state display delay time 5 130 260 ns 10 60 120 15 50 100 t thl t tlh output transition time 5 100 200 ns 10 50 100 15 40 80 t setup setup time data to clock t s(d) 5 0 -95 ns 10 0 -35 15 0 -20 setup time write enable to clock t s(we) 5 250 125 ns 10 100 50 15 70 35 setup time write address to clock t s(wa) 5 250 125 ns 10 100 50 15 70 35 t r, t s clock rise and fall time 5 15 ns 10 5 15 5 t hold hold time data to clock t s(d) 5220110 ns 10 100 50 15 80 40 hold time write enable to clock t s(we) 5 270 135 ns 10 130 65 15 80 40 hold time write address to clock t s(wa) 5 330 165 ns 10 140 70 15 90 45 t w clock pulse width clock or write enable t w(cl) 5 350 175 ns 10 130 65 15 90 45 t w clock pulse width write address t w(wa) 5 300 150 ns 10 150 75 15 90 45 f cl maximum clock input frequency 5 1.5 3 mhz 10 3.5 7 15 4.5 9
hcf40208b 8/11 test circuit c l = 50pf or equivalent (includes jig and probe capacitance) r l = 200k w r t = z out of pulse generator (typically 50 w ) waveform : enable and disable time test switch t plh , t phl open t pzl , t plz v dd t pzh , t phz v ss
hcf40208b 9/11 switching waveform
hcf40208b 10/11 dim. mm. inch min. typ max. min. typ. max. a 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 c 0.5 0.020 c1 45? (typ.) d 15.20 15.60 0.598 0.614 e 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 13.97 0.550 f 7.40 7.60 0.291 0.300 l 0.50 1.27 0.020 0.050 s ? (max.) so-24 mechanical data po13t f c l e a1 b1 a e d e3 b 24 13 112 c1 s a2 8
hcf40208b 11/11 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no res ponsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devi ces or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com

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